How to Setup the 8-bit Timers – Counter 0 and Counter 2
There are seven registers to each 8-bit timer that you will need to look at. The table below shows both 8-bit Counters and there related registers with descriptions of what each register stands for. Each register handles different aspects of the timer. Below we will go through what they are called and what each register is used for. As you will notice, Counter 0 and Counter 2 registers look very similar. The difference being whether it contains a 0 or a 2. This allows you to easly identify which register belongs to which Counter.
8-bit Timer Registers
| Counter 0 | Description | Counter 2 |
|---|
| TCCR0A | Timer/Counter Control Register A | TCCR2A |
| TCCR0B | Timer/Counter Control Register B | TCCR2B |
| TIMSK0 | Timer/Counter Interrupt Mask Register | TIMSK2 |
| TIFR0 | Timer/Counter Interrupt Flag Register | TIFR2 |
| TCNT0 | Timer/Counter Register (The Timer) | TCNT2 |
| OCR0A | Output Compare Register A | OCR2A |
| OCR0B | Output Compare Register B | OCR2B |
8-bit Timer Register Tables For Counter 0 & Counter 2
| TCCR0A | COM0A1 | COM0A0 | COM0B1 | COM0B0 | - | - | WGM01 | WGM00 |
|---|
| TCCR2A | COM2A1 | COM2A0 | COM2B1 | COM2B0 | - | - | WGM21 | WGM20 |
|---|
| Read/Write | R/W | R/W | R/W | R/W | R | R | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores Compare Output settings and 2 of the 3 Waveform Generation Mode settings. |
| TCCR0B | FOC0A | FOC0B | - | - | WGM02 | CS02 | CS01 | CS00 |
|---|
| TCCR2B | FOC2A | FOC2B | - | - | WGM22 | CS22 | CS21 | CS20 |
|---|
| Read/Write | W | W | R | R | R/W | R/W | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores A and B Force Output Compare bits, 1 of the 3 Waveform Generation Mode settings, and the Clock Speed Selection settings. |
| TIMSK0 | - | - | - | - | - | OCIE0B | OCIE0A | TOIE0 |
|---|
| TIMSK2 | - | - | - | - | - | OCIE2B | OCIE2A | TOIE2 |
|---|
| Read/Write | R | R | R | R | R | R/W | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores the Output Compare Match Interrupt Enable A and B bits and Timer Overflow Interrupt Enable bit |
| TIFR0 | - | - | - | - | - | OCF0B | OCF0A | TOV0 |
|---|
| TIFR2 | - | - | - | - | - | OCF2B | OCF2A | TOV2 |
|---|
| Read/Write | R | R | R | R | R | R/W | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores the Output Compare Match Flags A and B and Timer Overflow Interrupt flag |
Looking at registers TCCR0A and TCCR0B, we will start by setting bits, WGM02, WGM01 and WGM00 for Counter 0 and WGM22, WGM21 and WGM20 for Counter 2. These bits are used for setting what is called the Waveform Generation Mode (WGM). The table below shows you each mode that you can set your timer for and which bits you need to set to get the required mode. (Normal is set by default)
(PWM Type explaned here http://appusajeev.wordpress.com/2010/09/30/pwm-in-avr/)
Waveform Generation Mode (WGM):
| Mode | WGM02 | WGM01 | WGM00 | Description ( Counter 0 ) | TOP |
|---|
| Mode | WGM22 | WGM21 | WGM20 | Description ( Counter 2 ) | TOP |
|---|
| 0 | 0 | 0 | 0 | Normal | 0XFF |
| 1 | 0 | 0 | 1 | Phase Correct Pulse Width Modulation (PWM) | 0XFF |
| 2 | 0 | 1 | 0 | Clear Timer on Compare (CTC) | OCRA |
| 3 | 0 | 1 | 1 | Fast Pulse Width Modulation (PWM) | 0XFF |
| 4 | 1 | 0 | 0 | Reserved | - |
| 5 | 1 | 0 | 1 | Phase Correct Pulse Width Modulation (PWM) | OCRA |
| 6 | 1 | 1 | 0 | Reserved | - |
| 7 | 1 | 1 | 1 | Fast Pulse Width Modulation (PWM) | OCRA |
Now that you have picked the WGM mode you want (Normal, CTC, Phase Correct PWM, or Fast PWM), you will need to set the Compare Output Mode using one of the three sets of tables below. By default, it is set to normal port operation.
Compare Output Mode, Using non-PWM Mode (Normal / CTC)
| COM0A1 | COM0A0 | Description ( Counter 0 ) |
|---|
| COM2A1 | COM2A0 | Description ( Counter 2 ) |
|---|
| 0 | 0 | Normal port operation, OC0A / OC2A disconnected. |
| 0 | 1 | Toggle OC0A / OC2A on Compare Match |
| 1 | 0 | Clear OC0A / OC2A on Compare Match |
| 1 | 1 | Set OC0A / OC2A on Compare Match |
| COM0B1 | COM0B0 | Description ( Counter 0 ) |
|---|
| COM2B1 | COM2B0 | Description ( Counter 2 ) |
|---|
| 0 | 0 | Normal port operation, OC0B / OC2B disconnected. |
| 0 | 1 | Toggle OC0B / OC2B on Compare Match |
| 1 | 0 | Clear OC0B / OC2B on Compare Match |
| 1 | 1 | Set OC0B / OC2B on Compare Match |
Compare Output Mode, Using Fast PWM Pulse Width Modulation Mode
| COM0A1 | COM0A0 | Description ( Counter 0 ) |
|---|
| COM2A1 | COM2A0 | Description ( Counter 2 ) |
|---|
| 0 | 0 | Normal port operation, OC0A / OC2A disconnected. |
| 0 | 1 | WGM02 / WGM22 = 0: Normal Port Operation, OC0A / OC2A Disconnected.
WGM02 / WGM22 = 1: Toggle OC0A / OC2A on Compare Match. |
| 1 | 0 | Clear OC0A / OC2A on Compare MatchSet OC0A / OC2A at BOTTOM (non-inverting mode) |
| 1 | 1 | Set OC0A / OC2A on Compare MatchClear OC0A / OC2A at BOTTOM (inverting mode) |
| COM0B1 | COM0B0 | Description ( Counter 0 ) |
|---|
| COM2B1 | COM2B0 | Description ( Counter 2 ) |
|---|
| 0 | 0 | Normal port operation, OC0B / OC2B disconnected. |
| 0 | 1 | Reserved |
| 1 | 0 | Clear OC0B / OC2B on Compare MatchSet OC0B / OC2B at BOTTOM (non-inverting mode) |
| 1 | 1 | Set OC0B / OC2B on Compare MatchClear OC0B / OC2B at BOTTOM (inverting mode) |
Compare Output Mode, Using Phase Correct PWM Mode
| COM0A1 | COM0A0 | Description ( Counter 0 ) |
|---|
| COM2A1 | COM2A0 | Description ( Counter 2 ) |
|---|
| 0 | 0 | Normal port operation, OC0A / OC2A disconnected. |
| 0 | 1 | WGM22 = 0: Normal Port Operation, OC0A / OC2A Disconnected.
WGM22 = 1: Toggle OC0A / OC2A on Compare Match. |
| 1 | 0 | Clear OC0A / OC2A on Compare Match when up-counting.
Set OC0A / OC2A on Compare Match when down-counting |
| 1 | 1 | Set OC0A / OC2A on Compare Match when up-counting.
Clear OC0A / OC2A on Compare Match when down-counting. |
| COM0B1 | COM0B0 | Description ( Counter 0 ) |
|---|
| COM2B1 | COM2B0 | Description ( Counter 2 ) |
|---|
| 0 | 0 | Normal port operation, OC0B / OC2B disconnected. |
| 0 | 1 | Reserved |
| 1 | 0 | Clear OC0B / OC2B on Compare Match when up-counting.
Set OC0B / OC2B on Compare Match when down-counting |
| 1 | 1 | Set OC0B / OC2B on Compare Match when up-counting.
Clear OC0B / OC2B on Compare Match when down-counting. |
Note: When not using normal mode, you will need to set the Data Direction Register (DDR) bit corresponding to the Counters output pin you want to use.
| Counter 0 in register TCCR0A | Counter 2 in register TCCR2A |
|---|
| COM0A1 & COM0A0 | COM0B1 & COM0B0 | COM2A1 & COM2A0 | COM2B1 & COM2B0 |
| OC0A is PD6 (pin 6 on Port D) | OC0B is PD5 (pin 5 on Port D) | OC2A is PB3 (pin 3 on Port B) | OC2B is PD3 (pin 3 on Port D) |
Selecting the Speed at Which The Timer Runs At
By default the ATmega168 runs at 8MHz with the system clock. This means that the timer can be updated, up to 8,000,000 times per second. By setting bits CS02, CS01 and CS00 (that are in register TCCR0B for Counter 0), or setting bits CS22, CS21 and CS20 (that are in register TCCR2B for Counter 2), using the table below you can set the clock from off, which is the default setting, to the full 8mHz or slow down this rate with a prescaler.
Clock Speed Selection
| CS02 | CS01 | CS00 | Description ( Counter 0 ) |
|---|
| CS22 | CS21 | CS20 | Description ( Counter 2 ) |
|---|
| 0 | 0 | 0 | No clock source (Timer/Counter stopped) |
| 0 | 0 | 1 | Clock (No prescaling) |
| 0 | 1 | 0 | Clock/8 (From prescaler) |
| 0 | 1 | 1 | Clock/64 (From prescaler) |
| 1 | 0 | 0 | Clock/256 (From prescaler) |
| 1 | 0 | 1 | Clock/1024 (From prescaler) |
| 1 | 1 | 0 | External clock source on T0 pin. Clock on falling edge. |
| 1 | 1 | 1 | External clock source on T0 pin. Clock on rising edge. |
Optional Bit Settings
FOC0A / FOC0B Force Output Compare A and B (that are in register TCCR0B – Counter 0)
FOC2A / FOC2B Force Output Compare A and B (that are in register TCCR2B – Counter 2)
The FOC (FOC0A, FOC0B, FOC2A, FOC2B) bits are only active when the Waveform Generation Mode (WGM) is set to a non-PWM setting. However, when operating in PWM mode this bit must be set to zero when TCCR0B / TCCR2B is written to ensure compatibility with future devices. When the FOC bit is set to one, an immediate Compare Match is forced on the Waveform Generation unit. The FOC output is changed according to the settings of the Output Compare Match bits. The FOC bit is implemented as a strobe. Therefore the value present in the Output Compare Match bits determines the effect of the forced compare. A FOC strobe will not generate any interrupt, nor will it clear the timer in Clear Timer on Compare (CTC) mode using Output Compare Register as TOP. The FOC bit is always read as zero.
Timer/Counter Interrupts (Register TIMSK0 / TIMSK2)
OCIE0A / OCIE2A Timer/Counter Output Compare Match Interrupt Enable A
When the OCIE0A / OCIE2A bit is set to one the Timer/Counter Compare Match Interrupt A is enabled.
Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs.
(When the OCF0A / OCF2A bit is set in the Timer/Counter Interrupt Flag Register – TIFR0 / TIFR2)
OCIE0B / OCIE2B Timer/Counter Output Compare Match Interrupt Enable B
When the OCIE0B / OCIE2B bit is set to one, the Timer/Counter Compare Match Interrupt B is enabled.
Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs.
(When the OCF0B / OCF2B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0 / TIFR2)
TOIE0 / TOIE2 Timer/Counter Overflow Interrupt Enable
When the TOIE0 / TOIE2 bit is set to one, the Timer/Counter Overflow interrupt is enabled.
Once enabled, an interrupt will execute when an overflow in Timer/Counter occurs.
(When the TOV0 / TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR0 / TIFR2)
Interrupt Flag Register (Register TIFR0 / TIFR2)
OCF0A / OCF2A Timer/Counter Output Compare Match Flag A
The OCF0A / OCF2A bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0A / OCR2A (Output Compare Register A). OCF0A / OCF2A is cleared by hardware when executing the corresponding interrupt. OCF0A / OCF2A can also be cleared by writing a logic one to the flag.
OCF0B / OCF2B Timer/Counter Output Compare Match Flag B
The OCF0B / OCF2B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B / OCR2B (Output Compare Register B). OCF0B / OCF2B is cleared by hardware when executing the corresponding interrupt. OCF0B / OCF2B can also be cleared by writing a logic one to the flag.
TOV0 / TOV2 Timer/Counter Overflow Flag
The TOV0 / TOV2 bit is set when an overflow occurs in the Timer/Counter. TOV0 / TOV2 is cleared by hardware when executing the corresponding interrupt. TOV0 / TOV2 can also be cleared by writing a logic one to the flag.
Output Compare Registers
Counter 0 has two Output Compare Registers, A (OCR0A) and B (OCR0B).
Counter 2 has two Output Compare Registers, A (OCR2A) and B (OCR2B).
In each of these registers you set the valve you would like the Counter to generate an interrupt at.
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